7 search results - page 1 / 2 » Scalable and scalably-verifiable sequential synthesis |
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper describes an efficient implementation of an effective sequential synthesis operation that uses induction to detect and merge sequentially-equivalent nodes. State-encodi...
CAV
2010
Springer
13 years 5 months ago
2010
Springer
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transforma...
DATE
2009
IEEE
13 years 8 months ago
2009
IEEE
The process of sequential redundancy identification is the cornerstone of sequential synthesis and equivalence checking frameworks. The scalability of the proof obligations inhere...
DAC
2012
ACM
11 years 7 months ago
2012
ACM
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
FPGA
2009
ACM
13 years 11 months ago
2009
ACM
We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is cap...