35 search results - page 7 / 7 » Scan Test Planning for Power Reduction |
DAC
2005
ACM
13 years 7 months ago
2005
ACM
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
TC
2008
13 years 5 months ago
2008
A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during te...
DFT
1999
IEEE
13 years 9 months ago
1999
IEEE
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...
ATS
2005
IEEE
13 years 11 months ago
2005
IEEE
Abstract—This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within...
VLSID
2006
IEEE
13 years 11 months ago
2006
IEEE
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...