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2005
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Low Transition LFSR for BIST-Based Applications

9 years 9 months ago
Low Transition LFSR for BIST-Based Applications
Abstract—This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within random test pattern and between consecutive patterns. In other words, transitions are reduced in two dimensions, i.e. between consecutive patterns (fed to a combinational circuit) and consecutivebits (sent to a scan chain). LT-LFSR is independentof circuit under test and flexible to be used for both BIST and scan-based BIST architectures. The experimental results for ISCAS’85 and ’89 benchmarks, confirm up to 77% and 49% reduction in average and peak power, respectively.
Mohammad Tehranipoor, Mehrdad Nourani, Nisar Ahmed
Added 24 Jun 2010
Updated 24 Jun 2010
Type Conference
Year 2005
Where ATS
Authors Mohammad Tehranipoor, Mehrdad Nourani, Nisar Ahmed
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