61 search results - page 11 / 13 » Scan chain clustering for test power reduction |
DAC
2003
ACM
13 years 11 months ago
2003
ACM
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architect...
ICCD
2004
IEEE
14 years 2 months ago
2004
IEEE
Many test data compression schemes are based on LFSR reseeding. A drawback of these schemes is that the unspecified bits are filled with random values resulting in a large number ...
DAC
2005
ACM
13 years 7 months ago
2005
ACM
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
DFT
1999
IEEE
13 years 10 months ago
1999
IEEE
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...
ATS
2003
IEEE
13 years 11 months ago
2003
IEEE
: Most of the recently discussed test stimulus data compression techniques are based on the low care bit densities found in typical scan test vectors. Data reduction primarily is a...