43 search results - page 1 / 9 » Scheduling and resource binding for low power |
ISSS
1995
IEEE
13 years 9 months ago
1995
IEEE
Decisions taken at the earliest steps of the design process may have a significantimpact on the characteristics of the final implementation. This paper illustrates how power con...
ISSS
2000
IEEE
13 years 10 months ago
2000
IEEE
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...
ICCAD
2000
IEEE
13 years 10 months ago
2000
IEEE
— Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral l...
TVLSI
2010
13 years 6 days ago
2010
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...