50 search results - page 4 / 10 » Secure FPGA circuits using controlled placement and routing |
FPGA
2003
ACM
13 years 11 months ago
2003
ACM
The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently dev...
FPGA
2000
ACM
13 years 10 months ago
2000
ACM
In this paper we introduce a new Simulated Annealingbased timing-driven placement algorithm for FPGAs. This paper has three main contributions. First, our algorithm employs a nove...
DAC
2008
ACM
14 years 7 months ago
2008
ACM
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
FPL
2006
Springer
13 years 10 months ago
2006
Springer
We introduce a new congestion driven placement algorithm for FPGAs in which the overlappingeffect of boundingboxes is taken into consideration. Experimental results show that comp...
FPGA
2005
ACM
13 years 12 months ago
2005
ACM
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...