605 search results - page 2 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
GLVLSI
1998
IEEE
13 years 9 months ago
1998
IEEE
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
DAC
2003
ACM
13 years 10 months ago
2003
ACM
Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and timeto-ma...
APCSAC
2001
IEEE
13 years 9 months ago
2001
IEEE
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Exte...
TVLSI
2010
12 years 12 months ago
2010
Program code in a computer system can be altered either by malicious security attacks or by various faults in microprocessors. At the instruction level, all code modifications are ...