38 search results - page 2 / 8 » Serial-link bus: a low-power on-chip bus architecture |
TVLSI
2008
13 years 5 months ago
2008
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is proposed t...
CAL
2008
13 years 5 months ago
2008
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
Milenko Drinic UCLA Computer Science Dep. 4732 Boelter Hall Los Angeles, CA 90095-1596 milenko@cs.ucla.edu Darko Kirovski Microsoft Research One Microsoft Way Redmond, WA 98052 da...
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
This paper proposes a data encoder to reduce switched capacitance on system bus. Our method focuses on transferring raw video data (pixels) between off-chip memory and on-chip mem...