14 search results - page 2 / 3 » Simultaneous Analytic Area and Power Optimization for Repeat... |
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
This work first presents an analytical repeater insertion method which optimizes power under delay constraint for a single net. This method finds the optimal repeater insertion ...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
Repeaters are often used to drive high impedance interconnects. These lines have become highly inductive and can affect signal behavior. The line inductance should therefore be co...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
ITC
2002
IEEE
13 years 10 months ago
2002
IEEE
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
Buffer insertion method plays a great role in modern VLSI design. Many buffer insertion algorithms have been proposed in recent years. However, most of them used simplified delay ...