20 search results - page 2 / 4 » Simultaneous Gate Sizing and Fanout Optimization |
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm w...
ISPD
2009
ACM
13 years 11 months ago
2009
ACM
Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven h...
TVLSI
2008
13 years 4 months ago
2008
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
JCP
2008
13 years 4 months ago
2008
Sleep transistors in industrial power-gating designs are custom designed with an optimal size. Consequently, sleep transistor P/G network optimization becomes a problem of finding ...
PATMOS
2007
Springer
13 years 11 months ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...