25 search results - page 4 / 5 » Simultaneous Gate and Interconnect Sizing for Circuit-Level ... |
ISLPED
2007
ACM
13 years 7 months ago
2007
ACM
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
ICCAD
1991
IEEE
13 years 9 months ago
1991
IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
GLVLSI
2003
IEEE
13 years 11 months ago
2003
IEEE
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
—Designing high-performance systems with high yield under parameter variations has raised serious design challenges in nanometer technologies. In this paper, we propose a profit-...
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...