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JCP
2008
174views more  JCP 2008»
9 years 11 months ago
Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs
Sleep transistors in industrial power-gating designs are custom designed with an optimal size. Consequently, sleep transistor P/G network optimization becomes a problem of finding ...
Kaijian Shi, Zhian Lin, Yi-Min Jiang, Lin Yuan
DAC
2003
ACM
11 years 19 days ago
Distributed sleep transistor network for power reduction
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
Changbo Long, Lei He
ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
10 years 6 months ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...
DATE
2009
IEEE
111views Hardware» more  DATE 2009»
10 years 6 months ago
Enabling concurrent clock and power gating in an industrial design flow
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...
Leticia Maria Veiras Bolzani, Andrea Calimera, Alb...
ASPDAC
2004
ACM
126views Hardware» more  ASPDAC 2004»
10 years 5 months ago
High-level area and power-up current estimation considering rich cell library
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel,...
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