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FPL
2004
Springer
98views Hardware» more  FPL 2004»
13 years 10 months ago
Power-Driven Design Partitioning
In order to enable efficient integration of FPGAs into cost effective and reliable high-performance systems as well potentially into low power mobile systems, their power efficienc...
Rajarshi Mukherjee, Seda Ogrenci Memik
FPGA
1999
ACM
139views FPGA» more  FPGA 1999»
13 years 9 months ago
Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs
The demand for high-speed FPGA compilation tools has occurred for three reasons: first, as FPGA device capacity has grown, the computation time devoted to placement and routing h...
Yaska Sankar, Jonathan Rose
ICCAD
1995
IEEE
106views Hardware» more  ICCAD 1995»
13 years 8 months ago
Re-engineering of timing constrained placements for regular architectures
In a typical design ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...
Anmol Mathur, K. C. Chen, C. L. Liu
ICCAD
2003
IEEE
110views Hardware» more  ICCAD 2003»
14 years 2 months ago
Optimality and Stability Study of Timing-Driven Placement Algorithms
This work studies the optimality and stability of timing-driven placement algorithms. The contributions of this work include two parts: 1) We develop an algorithm for generating s...
Jason Cong, Michail Romesis, Min Xie
FPL
2005
Springer
114views Hardware» more  FPL 2005»
13 years 10 months ago
Post-Placement BDD-Based Decomposition for FPGAs
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...
Valavan Manohararajah, Deshanand P. Singh, Stephen...