78 search results - page 3 / 16 » Simultaneous buffer and wire sizing for performance and powe... |
ISQED
2002
IEEE
13 years 10 months ago
2002
IEEE
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
GLVLSI
2003
IEEE
13 years 11 months ago
2003
IEEE
Repeaters are often used to drive high impedance interconnects. These lines have become highly inductive and can affect signal behavior. The line inductance should therefore be co...
ICCAD
1996
IEEE
13 years 10 months ago
1996
IEEE
In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We de ne a class of optimization problems as CH-posynomial programs and reveal a genera...
DAC
2010
ACM
13 years 3 months ago
2010
ACM
Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. Ho...
ASPDAC
2009
ACM
13 years 9 months ago
2009
ACM
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...