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» Sleepy Stack Reduction of Leakage Power
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PATMOS
2004
Springer
13 years 10 months ago
Sleepy Stack Reduction of Leakage Power
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as...
Jun-Cheol Park, Vincent John Mooney III, Philipp P...
VLSI
2005
Springer
13 years 10 months ago
Pareto Points in SRAM Design Using the Sleepy Stack Approach
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption a...
Jun-Cheol Park, Vincent John Mooney III
VLSID
2005
IEEE
132views VLSI» more  VLSID 2005»
14 years 5 months ago
Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty
One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage r...
Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, ...
CF
2005
ACM
13 years 6 months ago
Drowsy region-based caches: minimizing both dynamic and static power dissipation
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
Michael J. Geiger, Sally A. McKee, Gary S. Tyson
HPCA
2009
IEEE
14 years 5 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...