36 search results - page 2 / 8 » Soft Error Rates with Inertial and Logical Masking |
DSD
2007
IEEE
13 years 11 months ago
2007
IEEE
With continuing increase in soft error rates, its foreseeable that multiple faults will eventually need to be considered when modeling circuit sensitivity and evaluating faulttole...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
— A radiation hardening technique for combinational logic circuits is described. The key idea is to exploit the asymmetric logical masking probabilities of gates, hardening gates...
ICCAD
2007
IEEE
14 years 2 months ago
2007
IEEE
Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...
DATE
2009
IEEE
14 years 2 days ago
2009
IEEE
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...