50 search results - page 9 / 10 » Soft Scheduling in High Level Synthesis |
CODES
2007
IEEE
14 years 15 days ago
2007
IEEE
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
ICCAD
2006
IEEE
14 years 3 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
DATE
2009
IEEE
14 years 28 days ago
2009
IEEE
Abstract - This paper describes an efficient graphbased method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common su...
DAC
2006
ACM
14 years 7 months ago
2006
ACM
Design space exploration during high level synthesis is often conducted through ad-hoc probing of the solution space using some scheduling algorithm. This is not only time consumi...
ASPDAC
2008
ACM
13 years 8 months ago
2008
ACM
We propose REWIRED (REgister Write Inhibition by REsource Dedication), a technique for reducing power during high level synthesis (HLS) by selectively inhibiting the storage of fun...