Minimizing concurrent test time in SoC's by balancing resource usage

We present a novel test scheduling algorithm for embedded corebased SoC’s. Given a system integrated with a set of cores and a set of test resources, we select a test for each core from a set of alternative test sets, and schedule it in a way that evenly balances the resource usage, and ultimately reduce the test application time. Furthermore, we propose a novel approach that groups the cores and assign higher priority to those with smaller number of alternate test sets. In addition, we also extend the algorithm to allow multiple test sets selection from a set of alternatives to facilitate testing for various fault models. Keywords System-on-a-chip test scheduling, resource balancing, test sets selection

• Type: Conference
• Year: 2002
• Where: GLVLSI
• Authors: Dan Zhao, Shambhu J. Upadhyaya, Martin Margala
• Keywords: GLVLSI 2002, Test Scheduling, Test Sets, Test Sets Selection, VLSI