19 search results - page 1 / 4 » Static power minimization in current-mode circuits |
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
ISCAS
1999
IEEE
13 years 9 months ago
1999
IEEE
Current mode (ECL) logic has long been the option of choice in those applications requiring logic functions at multigigahertz rates. This trend continues despite the obvious very ...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
-We propose a method involvingselectivesignalgating to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current ...
CF
2005
ACM
13 years 6 months ago
2005
ACM
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous a...