34 search results - page 3 / 7 » Statistical Analysis of Capacitance Coupling Effects on Dela... |
DAC
2006
ACM
14 years 6 months ago
2006
ACM
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
— With the transition to deep submicron technologies the density of on-chip interconnect lines has increased, together with the switching rate of the signals propagating along th...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
In signal integrity analysis, the joint effect of propagated noise through library cells, and of the noise injected on a quiet net by neighboring switching nets through coupling c...
TCAD
2010
13 years 4 months ago
2010
—With the scaling of complementary metal–oxide– semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacit...
DAC
1998
ACM
13 years 9 months ago
1998
ACM
Interconnect-driven optimization is an increasingly important step in high-performance design. Algorithms for buffer insertion have been successfully utilized to reduce delay in gl...