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DAC
2007
ACM
14 years 6 months ago
Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage
In this paper we address the the growing issue of junction tunneling leakage (Ijunc) at the circuit level. Specifically, we develop a fast approach to analyze the state-dependent ...
Tao Li, Zhiping Yu
DAC
2005
ACM
14 years 6 months ago
Full-chip analysis of leakage power under process variations, including spatial correlations
In this paper, we present a method for analyzing the leakage current, and hence the leakage power, of a circuit under process parameter variations that can include spatial correla...
Hongliang Chang, Sachin S. Sapatnekar
DATE
2005
IEEE
158views Hardware» more  DATE 2005»
13 years 10 months ago
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits
In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-toband-tunneling (BTBT) leakage, results in the large incr...
Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
DAC
2004
ACM
13 years 9 months ago
Leakage in nano-scale technologies: mechanisms, impact and design considerations
The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickne...
Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, K...
TCAD
2008
115views more  TCAD 2008»
13 years 5 months ago
Statistical Thermal Profile Considering Process Variations: Analysis and Applications
The nonuniform substrate thermal profile and process variations are two major concerns in the present-day ultradeep submicrometer designs. To correctly predict performance/ leakage...
Javid Jaffari, Mohab Anis