306 search results - page 4 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
DATE
2003
IEEE
13 years 11 months ago
2003
IEEE
Abstract — This paper defines a new diagnosis problem for diagnosing delay defects based upon statistical timing models. We illustrate the differences between the delay defect d...
IJCSS
2007
13 years 5 months ago
2007
This paper presents a low power driven synthesis framework for the unique class of nonregenerative Boolean Read-Once Functions (BROF). A two-pronged approach is adopted, where the...
VLSID
2002
IEEE
14 years 6 months ago
2002
IEEE
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
DAC
1997
ACM
13 years 9 months ago
1997
ACM
We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signa...
CMSB
2006
Springer
13 years 9 months ago
2006
Springer
Based on the logical description of gene regulatory networks developed by R. Thomas, we introduce an enhanced modelling approach that uses timed automata. It yields a refined quali...