Technology-Dependent Transformations for Low-Power Synthesis

We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signal arrival patterns, and signal probabilities are considered in reducing the switching activity-capacitance products. Power reduction up to 45.4% (average 12.4%) is achieved, with considerable improvements in area and delay, in preoptimized benchmarks. Also the effect of transformations on the random pattern testability of the circuits is studied.

• Type: Conference
• Year: 1997
• Where: DAC
• Authors: Rajendran Panda, Farid N. Najm
• Keywords: Computer Architecture, DAC 1997, Gate-level Logic Transformations, Random Pattern Testability, Signal Arrival Patterns