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ISQED
2007
IEEE
151views Hardware» more  ISQED 2007»
13 years 11 months ago
Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations
We propose gate level statistical simulation to bridge the gap between the most accurate Monte Carlo SPICE simulation and the most efficient circuit level statistical static timi...
Bao Liu
DATE
2000
IEEE
136views Hardware» more  DATE 2000»
13 years 9 months ago
Parametric Fault Simulation and Test Vector Generation
Process variation has forever been the major fail cause of analog circuit where small deviations in component values cause large deviations in the measured output parameters. This...
Khaled Saab, Naim Ben Hamida, Bozena Kaminska
ICCAD
1993
IEEE
100views Hardware» more  ICCAD 1993»
13 years 9 months ago
Macromodeling of the A.C. characteristics of CMOS Op-amps
An analytical-knowledge-based statistical method is developed to derive macromodels for the highly nonlinear A.C. response functions of CMOS Op-amp circuits. Simple circuit analys...
Pradip Mandal, V. Visvanathan
EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
13 years 9 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
PATMOS
2007
Springer
13 years 11 months ago
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits
Abstract. The continuous miniaturization of semiconductor devices imposes serious threats to design robustness against process variations and environmental fluctuations. Modern ci...
Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jia...