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» Statistical Timing Based Optimization using Gate Sizing
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DATE
2000
IEEE
85views Hardware» more  DATE 2000»
13 years 10 months ago
Gate Sizing Using a Statistical Delay Model
This paper is about gate sizing under a statistical delay model. It shows we can solve the gate sizing problem exactly for a given statistical delay model. The formulation used al...
E. T. A. F. Jacobs, Michel R. C. M. Berkelaar
VLSID
2005
IEEE
150views VLSI» more  VLSID 2005»
14 years 6 months ago
Multivariate Normal Distribution Based Statistical Timing Analysis Using Global Projection and Local Expansion
This paper employs general multivariate normal distribution to develop a new efficient statistical timing analysis methodology. The paper presents the theoretical framework of the...
Baohua Wang, Pinaki Mazumder
TCAD
2008
172views more  TCAD 2008»
13 years 5 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
PATMOS
2007
Springer
13 years 12 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...
ASPDAC
2008
ACM
122views Hardware» more  ASPDAC 2008»
13 years 7 months ago
Total power optimization combining placement, sizing and multi-Vt through slack distribution management
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...
Tao Luo, David Newmark, David Z. Pan