73 search results - page 4 / 15 » Steiner network construction for timing critical nets |
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
ISVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
- This paper presents a solution to the problem of designing interconnects for memory devices. More precisely, it solves the automatic routing problem of memory peripheral circuits...
TCAD
2002
13 years 4 months ago
2002
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
BIOCOMP
2006
13 years 6 months ago
2006
Intracellular signaling pathways as well as the interactions and coordination that exist among them are complex and difficult to visualize and understand. Computer-based models of...