8 search results - page 1 / 2 » Structural Fault Based Specification Reduction for Testing A... |
ET
2002
13 years 5 months ago
2002
Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is prop...
DFT
2007
IEEE
13 years 11 months ago
2007
IEEE
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
ITC
1993
IEEE
13 years 9 months ago
1993
IEEE
ÐPseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detecta...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
We discuss fault equivalence and dominance relations for multiple output combinational circuits. The conventional definition for equivalence says that “Two faults are equivalen...