16 search results - page 3 / 4 » Synthesis of Asynchronous Circuits Using Early Data Validity |
ICCAD
1993
IEEE
13 years 10 months ago
1993
IEEE
We present a design style and synthesis algorithm that encompasses both asynchronous and synchronous state machines. Our proposed design style not only supports generalized “bur...
DATE
2007
IEEE
14 years 3 days ago
2007
IEEE
Multiple asynchronous clock domains have been increasingly employed in System-on-Chip (SoC) designs for different I/O interfaces. Functional validation is one of the most expensiv...
ICCAD
2007
IEEE
14 years 2 days ago
2007
IEEE
—In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamic...
ICCAD
2007
IEEE
13 years 9 months ago
2007
IEEE
Stepwise refinement is at the core of many approaches to synthesis and optimization of hardware and software systems. For instance, it can be used to build a synthesis approach for...
ENTCS
2008
13 years 5 months ago
2008
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...