56 search results - page 4 / 12 » Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply ... |
ISLPED
2004
ACM
13 years 11 months ago
2004
ACM
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
GLVLSI
2003
IEEE
13 years 11 months ago
2003
IEEE
With scaling down to deep submicron and nanometer technologies, noise immunity is becoming a metric of the same importance as power, speed, and area. Smaller feature sizes, low vo...
TVLSI
2008
13 years 6 months ago
2008
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
TIM
2010
13 years 26 days ago
2010
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
ENGL
2007
13 years 6 months ago
2007
—A 2.5V high precision BiCMOS bandgap reference with supply voltage range of 6V to 18V was proposed and realized. It could be applied to lots of Power Management ICs (Intergrated...