68 search results - page 2 / 14 » Synthesis of Power Efficient Systems-on-Silicon |
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
In this paper, we present a functional partitioning method for low power real-time distributed embedded systems whose constituent nodes are systems-on-a-chip (SOCs). The systemlev...
TVLSI
2010
12 years 12 months ago
2010
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propos...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
RTSS
1998
IEEE
13 years 9 months ago
1998
IEEE
The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-...