18 search results - page 2 / 4 » Synthesis-for-scan and scan chain ordering |
ICCD
2007
IEEE
14 years 2 months ago
2007
IEEE
Scan chains are widely used to improve the testability of IC designs. In traditional 2D IC designs, various design techniques on the construction of scan chains have been proposed...
ICCAD
2003
IEEE
14 years 2 months ago
2003
IEEE
Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
It has been proven that scan path is a potent hazard for secure chips. Scan based attacks have been recently demonstrated against DES or AES and several solutions have been presen...
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
ATS
2004
IEEE
13 years 9 months ago
2004
IEEE
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...