4887 search results - page 3 / 978 » System Level Design Using C |
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
ng precision of abstract SystemC models using the SystemC Verification Standard Franco Carbognani1 , Christopher K. Lennard2 , C. Norris Ip3 , Allan Cochrane2 , Paul Bates2 1 Caden...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
the interconnection among the IP cores with all description levels This paper presents an automatic interconnection rectification (AIR)technique to correct the misplaced interconne...
RTCSA
2007
IEEE
13 years 11 months ago
2007
IEEE
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
FPT
2005
IEEE
13 years 10 months ago
2005
IEEE
We describe a communication-centric design methodology with SystemC that allows for efficient FPGA prototype generation of transaction level models (TLM). Using a framework compr...