60 search results - page 2 / 12 » System level clock tree synthesis for power optimization |
ISSS
1996
IEEE
13 years 9 months ago
1996
IEEE
ICCAD
2010
IEEE
13 years 3 months ago
2010
IEEE
Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a l...
DAC
2005
ACM
13 years 7 months ago
2005
ACM
Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of th...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
The existence of non-uniform thermal gradients on the substrate in high performance IC’s can significantly impact the performance of global on-chip interconnects. This issue is...
TCAD
2010
13 years 5 days ago
2010
Clock mesh networks are well known for their variation tolerance. But their usage is limited to high-end designs due to the significantly high resource requirements compared to clo...