Sciweavers

7 search results - page 1 / 2
» System-Level SRAM Yield Enhancement
Sort
View
ISQED
2006
IEEE
94views Hardware» more  ISQED 2006»
13 years 10 months ago
System-Level SRAM Yield Enhancement
It is well known that SRAM constitutes a large portion of modern integrated circuits, with 80% or more of the total transistors being dedicated to SRAM in a typical processor or S...
Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park...
ATS
2005
IEEE
104views Hardware» more  ATS 2005»
13 years 10 months ago
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM
In this paper, we develop a method to analyze the probability of access failure in SRAM array (due to random Vt variation in transistors) by jointly considering variations in cell...
Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Ma...
ICCAD
2004
IEEE
97views Hardware» more  ICCAD 2004»
14 years 1 months ago
Statistical design and optimization of SRAM cell for yield enhancement
In this paper, we have analyzed ond modeled the fiilure probabilities ofSRAM cells due to process parameter variations. A method to predict the yield of a memoiy chip based on the...
Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaush...
DAC
2008
ACM
14 years 5 months ago
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array fo
: Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future universal memory. It combines the desirable attributes of current memory technologies such as SRA...
Jing Li, Charles Augustine, Sayeef S. Salahuddin, ...
TVLSI
2010
12 years 11 months ago
SRAM Read/Write Margin Enhancements Using FinFETs
Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve ...
Andrew Carlson, Zheng Guo, Sriram Balasubramanian,...