392 search results - page 1 / 79 » System-level power estimation and optimization |
VLSID
2005
IEEE
14 years 9 months ago
2005
IEEE
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
The clock tree is the interconnect net on Systems-on-Chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall powe...
ICCD
2007
IEEE
14 years 6 months ago
2007
IEEE
This paper presents a methodology to generate a hierarchy of power models for power estimation of custom hardware IP blocks, enabling a trade-off between power estimation accuracy...
VLSID
2007
IEEE
14 years 3 months ago
2007
IEEE
In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage power of a System on Chip (SoC). We propose a novel system level temperature aware a...
ICCD
1999
IEEE
14 years 1 months ago
1999
IEEE