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» System-level power estimation and optimization
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VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
10 years 6 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
DATE
2007
IEEE
109views Hardware» more  DATE 2007»
10 years 2 days ago
System level clock tree synthesis for power optimization
The clock tree is the interconnect net on Systems-on-Chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall powe...
Saif Ali Butt, Stefan Schmermbeck, Jurij Rosenthal...
ICCD
2007
IEEE
133views Hardware» more  ICCD 2007»
10 years 2 months ago
System level power estimation methodology with H.264 decoder prediction IP case study
This paper presents a methodology to generate a hierarchy of power models for power estimation of custom hardware IP blocks, enabling a trade-off between power estimation accuracy...
Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi,...
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
10 years 14 hour ago
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs
In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage power of a System on Chip (SoC). We propose a novel system level temperature aware a...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...
ICCD
1999
IEEE
64views Hardware» more  ICCD 1999»
9 years 10 months ago
Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study
William Fornaciari, Donatella Sciuto, Cristina Sil...
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