Sciweavers

82 search results - page 16 / 17
» SystemC transaction level models and RTL verification
Sort
View
CODES
2007
IEEE
13 years 12 months ago
ESL design and HW/SW co-verification of high-end software defined radio platforms
Multiple wireless technologies are converging to run on personal handhelds. The plethora of communication standards next to the cost issues of deeper submicron processing require ...
A. C. H. Ng, J. W. Weijers, Miguel Glassee, Thomas...
IFIP
2001
Springer
13 years 10 months ago
Functional Test Generation using Constraint Logic Programming
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
13 years 9 months ago
Utilizing Formal Assertions for System Design of Network Processors
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Fe...
FDL
2006
IEEE
13 years 11 months ago
MCF: A Metamodeling-based Visual Component Composition Framework
Reusing IP-cores to construct system models facilitated by automated generation of glue-logic, and automated composability checks can help designers to create efficient simulation...
Deepak Mathaikutty, Sandeep K. Shukla
CODES
2009
IEEE
14 years 11 days ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...