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» Techniques for Verifying Superscalar Microprocessors
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DFT
2008
IEEE
151views VLSI» more  DFT 2008»
13 years 8 months ago
Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller
This paper presents a concurrent error detection technique for the control logic of a modern microprocessor. Our method is based on execution time prediction for each instruction ...
Michail Maniatakos, Naghmeh Karimi, Yiorgos Makris...
APCSAC
2005
IEEE
13 years 11 months ago
Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures
Increasing microprocessor vulnerability to soft errors induced by neutron and alpha particle strikes prevents aggressive scaling and integration of transistors in future technologi...
Jie Hu, Greg M. Link, Johnsy K. John, Shuai Wang, ...
MICRO
2006
IEEE
127views Hardware» more  MICRO 2006»
14 years 5 days ago
A Predictive Performance Model for Superscalar Processors
Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed si...
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthav...
ISLPED
2005
ACM
87views Hardware» more  ISLPED 2005»
13 years 11 months ago
Runtime identification of microprocessor energy saving opportunities
High power consumption and low energy efficiency have become significant impediments to future performance improvements in modern microprocessors. This paper contributes to the so...
W. L. Bircher, M. Valluri, J. Law, L. K. John
DFT
2003
IEEE
142views VLSI» more  DFT 2003»
13 years 11 months ago
Exploiting Instruction Redundancy for Transient Fault Tolerance
This paper presents an approach for integrating fault-tolerance techniques into microprocessors by utilizing instruction redundancy as well as time redundancy. Smaller and smaller...
Toshinori Sato