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» Technology mapping for k m-macrocell based FPGAs
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FPGA
2000
ACM
125views FPGA» more  FPGA 2000»
13 years 9 months ago
Technology mapping for k/m-macrocell based FPGAs
In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. Each cell in this a...
Jason Cong, Hui Huang, Xin Yuan
FPGA
1998
ACM
160views FPGA» more  FPGA 1998»
13 years 9 months ago
A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs
In this paper, we present a new retiming-based technology mapping algorithm for look-up table-based eld programmable gate arrays. The algorithm is based on a novel iterative proce...
Peichen Pan, Chih-Chang Lin
GLVLSI
2009
IEEE
126views VLSI» more  GLVLSI 2009»
13 years 9 months ago
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs
Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to nd good network, enumerating all cuts with large size consumes run-tim...
Taiga Takata, Yusuke Matsunaga
FCCM
2005
IEEE
90views VLSI» more  FCCM 2005»
13 years 11 months ago
Optimizing Technology Mapping for FPGAs Using CAMs
Joshua M. Lucas, Raymond Hoare, Alex K. Jones
FPGA
2008
ACM
151views FPGA» more  FPGA 2008»
13 years 7 months ago
Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs
Look-up table based FPGAs have migrated from a niche technology for design prototyping to a valuable end-product component and, in some cases, a replacement for general purpose pr...
Michael T. Frederick, Arun K. Somani