30 search results - page 1 / 6 » Temperature- and Cost-Aware Design of 3D Multiprocessor Arch... |
DSD
2009
IEEE
13 years 11 months ago
2009
IEEE
— 3D stacked architectures provide significant benefits in performance, footprint and yield. However, vertical stacking increases the thermal resistances, and exacerbates tempe...
DAC
2011
ACM
12 years 4 months ago
2011
ACM
Existing thermal-aware 3D placement methods assume that the temperature of 3D ICs can be optimized by properly distributing the power dissipations, and ignoring the heat conductiv...
MJ
2011
12 years 11 months ago
2011
New tendencies envisage 2D/3D Multi-Processor System-On-Chip (MPSoC) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute...
ISCA
2006
IEEE
13 years 10 months ago
2006
IEEE
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...
DAC
2012
ACM
11 years 7 months ago
2012
ACM
In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce t...