7 search results - page 1 / 2 » Test Point Insertion that Facilitates ATPG in Reducing Test ... |
ITC
2002
IEEE
13 years 9 months ago
2002
IEEE
Efficient production testing is frequently hampered because current digital circuits require test sets which are too large. These test sets can be reduced significantly by means...
VTS
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
ITC
2002
IEEE
13 years 9 months ago
2002
IEEE
1 Scan based transition tests are added to improve the detection of speed failures using scan tests. Empirical data suggests that both data volume and application time, for transi...
DFT
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
With the advent of nanometer technologies, the design size of integrated circuits is getting larger and the operation speed is getting faster. As a consequence, test cost is becom...