145 search results - page 3 / 29 » Test Resource Partitioning and Optimization for SOC Designs |
VLSID
2002
IEEE
14 years 6 months ago
2002
IEEE
In this paper, we present a functional partitioning method for low power real-time distributed embedded systems whose constituent nodes are systems-on-a-chip (SOCs). The systemlev...
ICCAD
2001
IEEE
14 years 3 months ago
2001
IEEE
1 We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique ar...
IWSOC
2003
IEEE
13 years 11 months ago
2003
IEEE
CAD tools support is essential in the success of today digital system design methodologies. Unfortunately, most of the classical design tools do not take into account the possibil...
ISVLSI
2007
IEEE
14 years 11 days ago
2007
IEEE
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
DATE
2007
IEEE
14 years 13 days ago
2007
IEEE
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...