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» Test Strategies for Low Power Devices
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ATS
2005
IEEE
144views Hardware» more  ATS 2005»
13 years 10 months ago
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing
—Test application at reduced power supply voltage (low-voltage testing) or reduced temperature (low-temperature testing) can improve the defect coverage of a test set, particular...
Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Bec...
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
14 years 1 months ago
A Novel Low-Power Scan Design Technique Using Supply Gating
— Reduction in test power is important to improve battery life in portable devices employing periodic self-test, to increase reliability of testing and to reduce test-cost. In sc...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukh...
ATS
1998
IEEE
112views Hardware» more  ATS 1998»
13 years 9 months ago
Integrated Current Sensing Device for Micro IDDQ Test
A current sensing device, namely Hall Effect MOSFET (HEMOS) is proposed. It is experimentally shown that the HEMOS enables a non-contacting, and non-disturbing current measurement...
Koichi Nose, Takayasu Sakurai
ISCAS
2003
IEEE
156views Hardware» more  ISCAS 2003»
13 years 10 months ago
GNOMES: a testbed for low power heterogeneous wireless sensor networks
Continuing trends in sensor, semiconductor and communication systems technology (smaller, faster, cheaper) make feasible very dense networks of fixed and mobile wireless devices ...
Erik Welsh, Walt Fish, J. Patrick Frantz
DAC
2009
ACM
14 years 6 months ago
O-Router:an optical routing framework for low power on-chip silicon nano-photonic integration
In this work, we present a new optical routing framework, O-Router for future low-power on-chip optical interconnect integration utilizing silicon compatible nano-photonic devices...
Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, D...