8 search results - page 1 / 2 » Test Time Minimization for Hybrid BIST of Core-Based Systems |
ATS
2003
IEEE
13 years 10 months ago
2003
IEEE
DFT
2003
IEEE
13 years 10 months ago
2003
IEEE
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
DSD
2005
IEEE
13 years 10 months ago
2005
IEEE
1 This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detecte...
ITC
1998
IEEE
13 years 9 months ago
1998
IEEE
Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of large design spa...
ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
1 This paper describes a heuristic for system-on-chip test scheduling in an abort-on-fail context, where the test is terminated as soon as a defect is detected. We consider an hybr...