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» Test challenges for deep sub-micron technologies
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ICCAD
2000
IEEE
95views Hardware» more  ICCAD 2000»
13 years 9 months ago
Test of Future System-on-Chips
Spurred by technology leading to the availability of millions of gates per chip, system-level integration is evolving as a new paradigm, allowing entire systems to be built on a s...
Yervant Zorian, Sujit Dey, Mike Rodgers
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
13 years 11 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
AAAI
2007
13 years 7 months ago
The VITA Financial Services Sales Support Environment
Knowledge-based recommender technologies support customers and sales representatives in the identification of appropriate products and services. These technologies are especially ...
Alexander Felfernig, Klaus Isak, Kalman Szabo, Pet...
ITC
2003
IEEE
148views Hardware» more  ITC 2003»
13 years 10 months ago
HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk
As technology evolves into the deep sub-micron era, signal integrity problems are growing into a major challenge. An important source of signal integrity problems is the crosstalk...
Xiaoliang Bai, Sujit Dey, Angela Krstic
CCECE
2006
IEEE
13 years 11 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya