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DATE
2009
IEEE
112views Hardware» more  DATE 2009»
9 years 6 months ago
Test exploration and validation using transaction level models
—The complexity of the test infrastructure and test strategies in systems-on-chip approaches the complexity of the functional design space. This paper presents test design space ...
Michael A. Kochte, Christian G. Zoellin, Michael E...
CODES
2003
IEEE
9 years 5 months ago
Transaction level modeling: an overview
Recently, the transaction-level modeling has been widely referred to in system-level design community. However, the transaction-level models(TLMs) are not well defined and the us...
Lukai Cai, Daniel Gajski
IESS
2009
Springer
182views Hardware» more  IESS 2009»
8 years 9 months ago
Modeling Cache Effects at the Transaction Level
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...
Ardavan Pedram, David Craven, Andreas Gerstlauer
TECS
2008
122views more  TECS 2008»
8 years 11 months ago
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
Gunar Schirner, Rainer Dömer
DATE
2003
IEEE
117views Hardware» more  DATE 2003»
9 years 5 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen
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