83 search results - page 1 / 17 » Test point insertion based on path tracing |
VTS
1996
IEEE
13 years 9 months ago
1996
IEEE
This paper presents an innovative method for inserting test points in the circuit-under-test to obtain complete fault coverage for a specified set of test patterns. Rather than us...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
We propose a low-overhead scan design methodology which employs a new test point insertion technique to establish scan paths through the functional logic. The technique re-uses th...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
Increasing system complexity and test cost demands new system-level solutions for mixed-signal systems. In this paper, we present a testability analysis and DfT insertion methodol...
VTS
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
