72 search results - page 2 / 15 » Test register insertion with minimum hardware cost |
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper presents an approach to reduce interconnect cost by insertion of identity operations in a CDFG. Other than previous approaches, it is based on systematic pattern analys...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
As technology enters the nanometer territory, the antenna effect plays an important role in determining the yield and reliability of a VLSI circuit. Diode insertion and jumper in...
ATS
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
Increasing system complexity and test cost demands new system-level solutions for mixed-signal systems. In this paper, we present a testability analysis and DfT insertion methodol...
INTEGRATION
2006
13 years 4 months ago
2006
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...