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EURODAC
1994
IEEE
145views VHDL» more  EURODAC 1994»
10 years 2 months ago
Testability analysis and improvement from VHDL behavioral specifications
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
Xinli Gu, Krzysztof Kuchcinski, Zebo Peng
METRICS
2002
IEEE
10 years 3 months ago
Testability Analysis of a UML Class Diagram
Design-for-testability is a very important issue in software engineering. It becomes crucial in the case of OO designs where control flows are generally not hierarchical, but are d...
Benoit Baudry, Yves Le Traon, Gerson Sunyé
VLSID
2005
IEEE
140views VLSI» more  VLSID 2005»
10 years 11 months ago
Variable Resizing for Area Improvement in Behavioral Synthesis
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...
R. Gopalakrishnan, Rajat Moona
UML
2001
Springer
10 years 2 months ago
A UML-Based Approach to System Testing
System testing is concerned with testing an entire system based on its specifications. In the context of object-oriented, UML development, this means that system test requirements ...
Lionel C. Briand, Yvan Labiche
ASPDAC
1995
ACM
108views Hardware» more  ASPDAC 1995»
10 years 2 months ago
Synthesis-for-testability using transformations
- We address the problem of transforming a behavioral speciļ¬cation so that synthesis of a testable implementation from the new specification requires significantly less area and ...
Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy
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