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» Testing and built-in self-test - A survey
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VTS
1995
IEEE
99views Hardware» more  VTS 1995»
13 years 9 months ago
Arithmetic built-in self test for high-level synthesis
In this paper, we propose an entirely new Built-In Self Test scheme for high-level synthesis of data path architectures that makes use of the arithmetic blocks in the data path to...
Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerz...
ATS
2000
IEEE
149views Hardware» more  ATS 2000»
13 years 10 months ago
Efficient built-in self-test algorithm for memory
We present a new pseudorandom testing algorithm for the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are...
Sying-Jyan Wang, Chen-Jung Wei
ISCAS
2002
IEEE
81views Hardware» more  ISCAS 2002»
13 years 10 months ago
Low-voltage analog current detector supporting at-speed BIST
This paper presents a design of a low-voltage analog current detector supporting at-speed Built-In-Self-Test (BIST) methodology. In testing mode, the current detector performs a n...
Srdjan Dragic, Igor M. Filanovsky, Martin Margala
VTS
2002
IEEE
162views Hardware» more  VTS 2002»
13 years 10 months ago
Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus
Single-bit second-order delta-sigma modulators are commonly used in high-resolution ADCs. Testing this type of modulator requires a high-resolution test stimulus, which is diffic...
Chee-Kian Ong, Kwang-Ting (Tim) Cheng
CATA
2009
13 years 6 months ago
Built-in Self-Test for Memory Resources in Virtex-4 Field Programmable Gate Arrays
ABSTRACT: We present a Built-In Self-Test (BIST) approach for programmable embedded memories in Xilinx Virtex-4 Field Programmable Gate Arrays (FPGAs). The target resources are the...
Brooks R. Garrison, Daniel T. Milton, Charles E. S...