41 search results - page 2 / 9 » The Latency Hiding Effectiveness of Decoupled Access Execute... |
ISCA
1994
IEEE
13 years 9 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
ICS
2005
Tsinghua U.
13 years 11 months ago
2005
Tsinghua U.
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
CASES
2006
ACM
13 years 9 months ago
2006
ACM
Ever increasing performance requirements have elevated deeply pipelined architectures to a standard even in the embedded processor domain, requiring the incorporation of dynamic b...
DSD
2011
IEEE
12 years 5 months ago
2011
IEEE
Abstract—We present a new low-level interfacing scheme for connecting custom accelerators to processors that tolerates latencies that usually occur when accessing hardware accele...
IESS
2009
Springer
13 years 3 months ago
2009
Springer
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...